This disclosure relates to a receiving apparatus that receives serial data, or serial pattern, which includes a plurality of contiguous blocks each having a known bit pattern, or a specific pattern. The receiving apparatus detects that serial data including a predetermined number of contiguous blocks each having the specific pattern is received.
Various communication protocols used in high-speed serial communication technology assume detection of specific patterns. As illustrated in FIG. 15, a typical structure of serial pattern includes a preamble, a start delimiter, a payload, and an end of burst (EOB) (or end delimiter). Each of them except for the payload, which is used for carrying data, has a specific number of bits with a specific pattern specified in the communication protocols.
Japanese Laid-open Patent Publication JP 7-202865 (Patent document 1) describes a technique in which serial data is converted to n-bit parallel data. The n-bit parallel data is received and (n+m−1)-bit parallel data is stored in a register, where m is a length of a specific pattern. By successively shifting the start bit by one bit, N data each including M contiguous bits are read from the register in which (n+m−1)-bit parallel data is stored. And matching of the N data with the m-bit specific pattern is detected in parallel by using N m-bit comparators.
Japanese Laid-open Patent Publication JP 2005-260500 (Patent document 2) and Japanese Laid-open Patent Publication JP 8-65294 (Patent document 3) each describes a technique that permits bit errors caused by, for example, disturbances during transmission. That is, each bit in parallel data is compared with a corresponding bit in a specific pattern. Even when some bits in parallel data do not match corresponding bits in the specific pattern, it is determined that the parallel data matches the specific pattern if the number of unmatched bits does not exceed a predetermined value.
Each of the preamble and the end of burst, such as those defined in the standard specification IEEE802.3av for 10G-EPON applications, is composed of a plurality of contiguous blocks. Each of the blocks has a 66-bit specific pattern.
The technique disclosed in Patent Document 1 involves detecting the specific pattern in a block. However, the technique is not intended for receiving serial data that contains a plurality of successive blocks having specific patterns.
The techniques disclosed in Patent Documents 2 and 3 may be used to determine a number of bit errors in each block. However, neither of these Patent Documents discloses a technique to determine a total number of bit errors in successive blocks.